Virtual Memory and Paging Internals: How MMUs, Multi-Level Page Tables, and TLBs Power Operating Systems

Every user-space program running on modern operating systems operates under a master illusion: it believes it has exclusive access to a flat, unbroken, continuous span of hundreds of gigabytes (or exabytes) of memory, completely isolated from every other process on the machine. This fundamental abstraction is orchestrated by hardware-enforced Virtual Memory, driven by the CPU's Memory Management Unit (MMU) and multi-level page table traversals.

Without virtual memory, multi-tenant computing, process isolation, memory-mapped I/O, demand paging, and copy-on-write optimizations would be completely impossible. Here is what really happens inside silicon when your code dereferences a pointer.

The Canonical Address Space on x86-64

While x86-64 uses 64-bit pointers, modern hardware does not utilize all 64 bits for address translation. Standard architectures use 48-bit virtual addressing (allowing 256 Terabytes of space) or 5-level paging with 57-bit addressing (128 Petabytes). Pointers must be in canonical form: bit 47 must be sign-extended through bits 48 to 63.

+-------------------------------------------------------------------------+
|             48-BIT CANONICAL VIRTUAL ADDRESS DECOMPOSITION              |
+-------------------------------------------------------------------------+

  63        48 47     39 38     30 29     21 20     12 11                0
 +------------+---------+---------+---------+---------+--------------------+
 | Sign Ext   |  PML4   |  PDPT   |   PD    |   PT    |   Physical Offset  |
 | (16 bits)  | (9 bits)| (9 bits)| (9 bits)| (9 bits)|     (12 bits)      |
 +------------+---------+---------+---------+---------+--------------------+
       │           │         │         │         │              │
       │           ▼         ▼         ▼         ▼              │
       │       Index into Index     Index     Index             │
       │       Level 4    into L3   into L2   into L1           │
       │                                                        │
       └────────────────────────────────────────────────────────┼─────┐
                                                                │     │
                                                                ▼     ▼
                                                       [ Physical 4KB Page Frame ]

The 4-Level Page Table Walk: Walking the Tree

When an instruction like mov rax, [rdi] executes, the CPU’s hardware Memory Management Unit must resolve the virtual address into a physical DRAM frame address:

1. CR3 Register: The base physical address of the current process's Page Map Level 4 (PML4) table is loaded into the CPU's CR3 register during every process context switch.
2. PML4 Lookup: The MMU extracts bits 47–39 (9 bits = 512 entries of 8 bytes = exactly one 4KB page). This identifies the Page Directory Pointer Table (PDPT).
3. PDPT Lookup: Bits 38–30 index the Page Directory Pointer Table, pointing to the Page Directory (PD).
4. PD Lookup: Bits 29–21 index the Page Directory, pointing to the Page Table (PT).
5. Page Table (PT) Entry: Bits 20–12 index the Page Table, retrieving the physical Base Address of the 4KB memory frame.
6. Offset Resolution: Bits 11–0 (12 bits = 4096 bytes) are concatenated to the base physical address to pinpoint the exact byte in physical RAM.

The Memory Latency Crisis: A 4-level table walk requires four separate memory lookups just to read a single byte of application data! Without hardware caching, memory access speeds would plummet by 80% to 90%.

Translation Lookaside Buffer (TLB) and TLB Shootdowns

To eliminate the crippling cost of walking page tables on every instruction, CPU designers introduced the Translation Lookaside Buffer (TLB): an associative, ultra-fast hardware cache situated directly inside the CPU core. A TLB lookup completes in a fraction of a nanosecond.

However, when an operating system alters or frees page mappings (for example, unmapping memory via munmap() or swapping pages to NVMe disk), the TLB entries across all active CPU cores become stale. The kernel must execute a TLB Shootdown:

/* Linux Kernel Architecture: TLB Invalidation Flow across SMP Cores */
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) {
    // 1. Invalidate local CPU core's TLB entry
    __native_flush_tlb_single(addr);

    // 2. Broadcast Inter-Processor Interrupt (IPI) to all other active cores
    smp_call_function_many(mm_cpumask(vma->vm_mm), 
                           do_flush_tlb_ipi, 
                           NULL, 1);
}

TLB shootdowns trigger hardware Inter-Processor Interrupts (IPIs) that force other cores to halt instruction pipelines and flush their translation registers, introducing measurable latency spikes in heavily multi-threaded workloads.

Major vs Minor Page Faults

When the CPU attempts to access a virtual address that has no valid mapping in the page table (or whose access permissions violate user privilege), the MMU halts execution and triggers a CPU Exception 14: Page Fault.

Hugepages: Mitigating TLB Thrashing in High-Performance Systems

By default, x86-64 operates on 4 Kilobyte page frames. An enterprise database caching 128 Gigabytes of memory requires over 33 million individual page entries! Because modern L1/L2 TLBs can only cache between 1,000 and 2,000 entries, the CPU experiences perpetual TLB misses.

Operating systems bypass this bottleneck using Hugepages (2 Megabyte or 1 Gigabyte pages):

• 2MB Pages: Translation stops at the Page Directory (PD) level; the PD entry directly points to a contiguous 2MB physical block, reducing page table depth from 4 to 3 levels.
• 1GB Pages: Translation stops at the Page Directory Pointer Table (PDPT) level, reducing depth to 2 levels.
• Result: A single TLB entry now covers 512 times more memory, eliminating TLB thrashing in Redis, PostgreSQL, and high-throughput vector search databases.

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